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FEATURES Signal-to-Noise Ratio: 69 dB @ f IN = 31 MHz Spurious-Free Dynamic Range: 85 dB @ fIN = 31 MHz Intermodulation Distortion of -75 dBFS @ fIN = 140 MHz ENOB = 11.1 @ fIN = 10 MHz Low-Power Dissipation: 475 mW No Missing Codes Guaranteed Differential Nonlinearity Error: 0.6 LSB Integral Nonlinearity Error: 0.6 LSB Clock Duty Cycle Stabilizer Patented On-Chip Sample-and-Hold with Full Power Bandwidth of 750 MHz Straight Binary or Two's Complement Output Data 28-Lead SSOP, 48-Lead LQFP Single 5 V Analog Supply, 3 V/5 V Driver Supply Pin-Compatible to AD9220, AD9221, AD9223, AD9224, AD9225
VINA VINB
Complete 12-Bit, 65 MSPS ADC Converter AD9226
FUNCTIONAL BLOCK DIAGRAM
CLK AVDD DRVDD DUTY CYCLE STABILIZER SHA MDAC1 A/D CAPT CAPB VREF SENSE REF SELECT 1V MODE SELECT MODE AVSS CALIBRATION ROM 4 16 CORRECTION LOGIC 12 OUTPUT BUFFERS 3 8-STAGE 1-1/2-BIT PIPELINE A/D
AD9226
DRVSS
OTR BIT 1 (MSB) BIT 12 (LSB)
REFCOM
PRODUCT DESCRIPTION
The AD9226 is a monolithic, single-supply, 12-bit, 65 MSPS analog-to-digital converter with an on-chip, high-performance sample-and-hold amplifier and voltage reference. The AD9226 uses a multistage differential pipelined architecture with a patented input stage and output error correction logic to provide 12-bit accuracy at 65 MSPS data rates. There are no missing codes over the full operating temperature range (guaranteed). The input of the AD9226 allows for easy interfacing to both imaging and communications systems. With a truly differential input structure, the user can select a variety of input ranges and offsets including single-ended applications. The sample-and-hold amplifier (SHA) is well suited for IF undersampling schemes such as in single-channel communication applications with input frequencies up to and well beyond Nyquist frequencies. The AD9226 has an on-board programmable reference. For system design flexibility, an external reference can also be chosen. A single clock input is used to control all internal conversion cycles. An out-of-range signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow.
The AD9226 has two important mode functions. One will set the data format to binary or two's complement. The second will make the ADC immune to clock duty cycle variations.
PRODUCT HIGHLIGHTS
IF Sampling--The patented SHA input can be configured for either single-ended or differential inputs. It will maintain outstanding AC performance up to input frequencies of 300 MHz. Low Power--The AD9226 at 475 mW consumes a fraction of the power presently available in existing, high-speed monolithic solutions. Out of Range (OTR)--The OTR output bit indicates when the input signal is beyond the AD9226's input range. Single Supply--The AD9226 uses a single 5 V power supply simplifying system power supply design. It also features a separate digital output driver supply line to accommodate 3 V and 5 V logic families. Pin Compatibility--The AD9226 is similar to the AD9220, AD9221, AD9223, AD9224, and AD9225 ADCs. Clock Duty Cycle Stabilizer--Makes conversion immune to varying clock pulsewidths.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD9226-SPECIFICATIONS
DC SPECIFICATIONS noted.)
Parameter
RESOLUTION ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) No Missing Codes Guaranteed Zero Error Gain Error TEMPERATURE DRIFT Zero Error Gain Error1 Gain Error2 POWER SUPPLY REJECTION AVDD (5 V 0.25 V) INPUT REFERRED NOISE VREF = 1.0 V VREF = 2.0 V ANALOG INPUT Input Span (VREF = 1 V) (VREF = 2 V) Input (VINA or VINB) Range Input Capacitance INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2.0 V Mode) Output Voltage Tolerance (2.0 V Mode) Output Current (Available for External Loads) Load Regulation3 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Current IAVDD4 IDRVDD5 POWER CONSUMPTION
4, 5
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, Differential inputs, TMIN to TMAX unless otherwise
Temp Test Level Min 12 Full 25C Full 25C Full Full 25C 25C Full Full Full Full Full 25C Full Full Full Full Full Full Full 25C Full 25C Full Full 25C Full V I V I I V I I V V V V V I V V V V IV V V I V I V V I V 0.6 0.6 12 0.3 0.6 2 26 0.4 0.05 1.4 2.0 Typ Max Unit Bits LSB LSB LSB LSB Bits % FSR % FSR % FSR % FSR ppm/C ppm/C ppm/C % FSR % FSR LSB rms LSB rms V p-p V p-p V pF V mV V mV mA mV mV k
1.6 1.0
0.4
0.5 0.25 1 2 0 7 1.0 15 2.0 29 1.0 0.7 1.5 5 AVDD
Full Full Full 25C Full 25C Full 25C
V V V I V I V I
4.75 2.85
5
5.25 5.25
V ( 5% AVDD Operating) V ( 5% DRVDD Operating) mA (2 V External VREF) mA (2 V External VREF) mA (2 V External VREF) mA (2 V External VREF) mW (2 V External VREF)
86 90.5 14.6 16.5 475 500
NOTES 1 Includes internal voltage reference error. 2 Excludes internal voltage reference error. 3 Load regulation with 1 mA load current (in addition to that required by the AD9226). 4 AVDD = 5 V 5 DRVDD = 3 V Specifications subject to change without notice.
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AD9226 DIGITAL SPECIFICATIONS (AVDD = 5 V, DRVDD = 3 V, f
Parameters LOGIC INPUTS (Clock, DFS , Duty Cycle , and Output Enable1) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current (VIN = AVDD) Low-Level Input Current (VIN = 0 V) Input Capacitance Output Enable1 LOGIC OUTPUTS (With DRVDD = 5 V) High-Level Output Voltage (IOH = 50 A) High-Level Output Voltage (IOH = 0.5 mA) Low-Level Output Voltage (IOL = 1.6 mA) Low-Level Output Voltage (IOL = 50 A) Output Capacitance LOGIC OUTPUTS (With DRVDD = 3 V) High-Level Output Voltage (IOH = 50 A) High-Level Output Voltage (IOH = 0.5 mA) Low-Level Output Voltage (IOL = 1.6 mA) Low-Level Output Voltage (IOL = 50 A)
NOTES 1 LQFP package. Specifications subject to change without notice.
1 1
SAMPLE
= 65 MSPS, VREF = 2.0 V, TMIN to TMAX, unless otherwise noted.)
Min Typ Max Unit
Temp
Test Level
Full Full Full Full Full Full
IV IV IV IV V IV
2.4 -10 -10 5 DRVDD - 0.5 2 4.5 2.4 0.4 0.1 5 DRVDD + 0.5 2 0.8 +10 +10
V V A A pF V
Full Full Full Full
IV IV IV IV
V V V V pF V V V V
Full Full Full Full
IV IV IV IV
2.95 2.80 0.4 0.05
SWITCHING SPECIFICATIONS
Parameters Max Conversion Rate Clock Period1 CLOCK Pulsewidth High2 CLOCK Pulsewidth Low2 Output Delay Pipeline Delay (Latency) Output Enable Delay3
(TMIN to TMAX with AVDD = 5 V, DRVDD = 3 V, CL = 20 pF)
Temp Full Full Full Full Full Full Full Test Level VI V V V V V V Min 65 15.38 3 3 3.5 7 15 Typ Max Unit MHz ns ns ns ns Clock Cycles ns
7
NOTES 1 The clock period may be extended to 10 s without degradation in specified performance @ 25C. 2 When MODE pin is tied to AVDD or grounded, the AD9226 SSOP is not affected by clock duty cycle. 3 LQFP package. Specifications subject to change without notice.
n+1 ANALOG INPUT n
n+2 n+3 n+4 n+5 n+7 n+6 n+8
CLOCK
DATA OUT
n-8
n-7
n-6
n-5
n-4
n-3
n-2
n-1
n
n+1
TOD = 7.0 MAX 3.5 MIN
Figure 1. Timing Diagram
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AD9226-SPECIFICATIONS
AC SPECIFICATIONS
Parameter SIGNAL-TO-NOISE RATIO fIN = 2.5 MHz fIN = 15 MHz fIN = 31 MHz fIN = 60 MHz fIN = 200 MHz1 SIGNAL-TO-NOISE RATIO AND DISTORTION fIN = 2.5 MHz fIN = 15 MHz fIN = 31 MHz fIN = 60 MHz fIN = 200 MHz1 TOTAL HARMONIC DISTORTION fIN = 2.5 MHz fIN = 15 MHz fIN = 31 MHz fIN = 60 MHz fIN = 200 MHz1 SECOND AND THIRD HARMONIC DISTORTION fIN = 2.5 MHz fIN = 15 MHz fIN = 31 MHz fIN = 60 MHz fIN = 200 MHz1 SPURIOUS FREE DYNAMIC RANGE fIN = 2.5 MHz fIN = 15 MHz fIN = 31 MHz fIN = 60 MHz fIN = 200 MHz1 ANALOG INPUT BANDWIDTH
NOTES 1 1.0 V Reference and Input Span Specifications subject to change without notice.
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, Differential Input unless otherwise noted.)
Temp Full
25C
Test Level V I V I V V V V I V I V V V V I V I V V V V I V I V V V V I V I V V V V
Min
Typ 68.9
Max
Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc MHz
68 68.4 67.4 68 68 65 68.8 67.9 68.3 67.3 67 67 60 -84 -77.0 -82.3 -76.0 -68 -68 -61 -86.5 -78 -86.7 -76 -83 -82 -75 86.4 78 85.5 76 82 81 60 750
Full
25C
Full Full Full Full
25C
Full
25C
Full Full Full Full
25C
Full
25C
Full Full Full Full
25C
Full
25C
Full Full Full Full
25C
Full
25C
Full Full Full 25C
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AD9226
EXPLANATION OF TEST LEVELS Test Level ABSOLUTE MAXIMUM RATINGS 1
I.
100% production tested.
Pin Name
With Respect to
Min -0.3 -0.3 -0.3 -6.5 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -65
Max +6.5 +6.5 +0.3 +6.5 +0.3 AVDD + 0.3 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 150 +150 300
Unit V V V V V V V V V V V V V V C C C
II. 100% production tested at 25C and sample tested at specified temperatures. AC testing done on sample basis. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. All devices are 100% production tested at 25C; sample tested at temperature extremes.
AVDD AVSS DRVDD DRVSS AVSS DRVSS AVDD DRVDD REFCOM AVSS CLK, MODE AVSS Digital Outputs DRVSS VINA, VINB AVSS VREF AVSS SENSE AVSS CAPB, CAPT AVSS OEB2 DRVSS CM LEVEL2 AVSS AVSS VR2 Junction Temperature Storage Temperature Lead Temperature (10 sec)
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2 LQFP package.
THERMAL RESISTANCE
JC SSOP JA SSOP JC LQFP JA LQFP
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.3C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76.2C/W
ORDERING GUIDE
Model AD9226ARS AD9226AST AD9226-EB AD9226-LQFP-EB
Temperature Range -40C to +85C -40C to +85C
Package Description 28-Lead Shrink Small Outline (SSOP) 48-Lead Thin Plastic Quad Flatpack (LQFP) Evaluation Board (SSOP) Evaluation Board (LQFP)
Package Option RS-28 ST-48
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9226 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD9226
PIN CONNECTION 48-Lead LQFP
MODE1 CAPT CAPT CAPB CAPB REF COM (AVSS)
PIN CONNECTION 28-Lead SSOP
CLK (LSB) BIT 12 BIT 11 VREF BIT 10 BIT 9 BIT 8
36 35 34
1 2 3 4 5 6 7
28 27 26 25 24
DRVDD DRVSS AVDD AVSS VINB VINA
48 47 46 45 44 43 42 41 40 39 38 37
VINB VINA CM LEVEL NC
VR
AVSS AVSS AVDD AVDD
1 2 3 4 PIN 1 IDENTIFIER
SENSE
AD9226
23
BIT 7 BIT 6 BIT 5
NC 5 NC 6 CLK 7 NC 8 OEB 9 NC 10 NC 11 (LSB) BIT 12 12 NC = NO CONNECT
AD9226
TOP VIEW (Not to Scale)
MODE2 AVDD 33 AVSS 32 AVSS
31
TOP VIEW 22 MODE 8 (Not to Scale) 21 CAPT
9 20 19 18 17 16 15
CAPB REFCOM (AVSS) VREF SENSE AVSS AVDD
BIT 4 10 BIT 3 11 BIT 2 12 (MSB) BIT 1 13 OTR 14
AVDD 30 DRVSS
29 28
DRVDD OTR 27 BIT 1 (MSB)
BIT 2 25 BIT 3
26 13 14 15 16 17 18 19 20 21 22 23 24
BIT 11
DRVSS DRVDD BIT 10 BIT 9
DRVDD BIT 4
DRVSS
BIT 8 BIT 7 BIT 6 BIT 5
48-PIN FUNCTION DESCRIPTIONS
28-PIN FUNCTION DESCRIPTIONS
Pin Number 1, 2, 32, 33 3, 4, 31, 34 5, 6, 8, 10, 11, 44 7 9 12 13 14, 22, 30 15, 23, 29 16-21, 24-26 27 28 35 36 37 38 39, 40 41, 42 43 45 46 47 48
Name AVSS AVDD NC CLK OEB BIT 12 BIT 11 DRVSS DRVDD BITS 10-5, BITS 4-2 BIT 1 OTR MODE2 SENSE VREF REFCOM (AVSS) CAPB CAPT MODE1 CM LEVEL VINA VINB VR
Description Analog Ground 5 V Analog Supply No Connect Clock Input Pin Output Enable (Active Low) Least Significant Data Bit (LSB) Data Output Bit Digital Output Driver Ground 3 V to 5 V Digital Output Driver Supply Data Output Bits Most Significant Data Bit (MSB) Out of Range Data Format Select Reference Select Reference In/Out Reference Common Noise Reduction Pin Noise Reduction Pin Clock Stabilizer Midsupply Reference Analog Input Pin (+) Analog Input Pin (-) Noise Reduction Pin
Pin Number 1 2 3-12 13 14 15, 26 16, 25 17 18 19 20 21 22 23 24 27 28
Name CLK BIT 12 BITS 11-2 BIT 1 OTR AVDD AVSS SENSE VREF REFCOM (AVSS) CAPB CAPT MODE VINA VINB DRVSS DRVDD
Description Clock Input Pin Least Significant Data Bit (LSB) Data Output Bits Most Significant Data Bit (MSB) Out of Range 5 V Analog Supply Analog Ground Reference Select Input Span Select (Reference I/O) Reference Common Noise Reduction Pin Noise Reduction Pin Data Format Select /Clock Stabilizer Analog Input Pin (+) Analog Input Pin (-) Digital Output Driver Ground 3 V to 5 V Digital Output Driver Supply
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AD9226
DEFINITIONS OF SPECIFICATIONS INTEGRAL NONLINEARITY (INL) EFFECTIVE NUMBER OF BITS (ENOB)
INL refers to the deviation of each individual code from a line drawn from "negative full scale" through "positive full scale." The point used as "negative full scale" occurs 1/2 LSB before the first code transition. "Positive full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, N = (SINAD - 1.76)/6.02 it is possible to obtain a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.
TOTAL HARMONIC DISTORTION (THD)
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges.
ZERO ERROR
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
The major carry transition should occur for an analog value 1/2 LSB below VINA = VINB. Zero error is defined as the deviation of the actual transition from that point.
GAIN ERROR
SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.
TEMPERATURE DRIFT
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
ENCODE PULSEWIDTH DUTY CYCLE
The temperature drift for zero error and gain error specifies the maximum change from the initial (25C) value to the value at TMIN or TMAX.
POWER SUPPLY REJECTION
Pulsewidth high is the minimum amount of time that the clock pulse should be left in the logic "1" state to achieve rated performance; pulsewidth low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specs define an acceptable clock duty cycle.
MINIMUM CONVERSION RATE
The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
MAXIMUM CONVERSION RATE
The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit.
APERTURE JITTER
The encode rate at which parametric testing is performed.
OUTPUT PROPAGATION DELAY
Aperture jitter is the variation in aperture delay for successive samples and can be manifested as noise on the input to the ADC.
APERTURE DELAY
The delay between the clock logic threshold and the time when all bits are within valid logic levels.
TWO TONE SFDR
Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) RATIO
The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).
S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
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AD9226
DRVDD DRVDD DRVDD AVDD
DRVSS DRVSS
AVSS
a. D0-D11, OTR
b. Three-State (OEB)
c. CLK
AVDD AVDD
AVSS AVSS
d. AIN
e. CAPT, CAPB, MODE, SENSE, VREF Figure 2. Equivalent Circuits
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Typical Performance Characteristics-AD9226
(AVDD = 5.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS with CLK Stabilizer Enabled, TA = 25 C, 2 V Differential Input Span, VCM = 2.5 V, AIN = -0.5 dBFS, VREF = 2.0 V, unless otherwise noted.)
0 -10 -20 -30 -40 SNR = 69.9dBc SINAD = 69.8dBc ENOB = 11.4BITS THD = -86.4dBc SFDR = 88.7dBc
100 SFDR - dBFS 90
dBFS AND dBc
80 SFDR - dBc 70 SNR - dBFS
dBFS
-50 -60 -70 -80 -90 -100 -110 -120 0 6.5 13 19.5 26 32.5
60 SNR - dBc 50
40 -30
-25
-20
-15 AIN - dBFS
-10
-5
0
FREQUENCY - MHz
TPC 1. Single-Tone 8K FFT with fIN = 5 MHz
TPC 4. Single-Tone SNR/SFDR vs. AIN with fIN = 5 MHz
0 -10 -20 -30 SNR = 70.4dBFS SFDR = 87.5dBFS
100 SFDR - dBFS 90 SFDR - dBc
dBFS AND dBc
-40
80 SNR - dBFS 70
dBFS
-50 -60 -70 -80 -90 -100 -110 -120 0 6.5 13 19.5 26 32.5
60 SNR - dBc 50
40 -30
-25
-20
-15 AIN - dBFS
-10
-5
0
FREQUENCY - MHz
TPC 2. Dual-Tone 8K FFT with fIN-1 = 18 MHz and fIN-2 = 20 MHz (AIN-1 = AIN-2 = -6.5 dBFS)
TPC 5. Dual-Tone SNR/SFDR vs. AIN with fIN-1 = 18 MHz and fIN-2 = 20 MHz
0 -10 -20 -30 -40 SNR = 69.5dBc SINAD = 69.4dBc ENOB = 11.3BITS THD = -85dBc SFDR = 87.6dBc
100 SFDR - dBFS 90
dBFS
-50 -60 -70 -80 -90 -100 -110 -120 0 6.5 13 19.5 26 32.5
dBFS AND dBc
80
SNR - dBFS
70
60 SFDR - dBc 50 SNR - dBc
40 -30
-25
-20
-15 AIN - dBFS
-10
-5
0
FREQUENCY - MHz
TPC 3. Single-Tone 8K FFT with fIN = 31 MHz
TPC 6. Single-Tone SNR/SFDR vs. AIN with fIN = 31 MHz
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AD9226
75 2V SPAN, DIFFERENTIAL 70 1V SPAN, DIFFERENTIAL 65
SINAD - dBc
12.2
71 70 2V SPAN, DIFFERENTIAL
11.4
69 68
ENOB - Bits SNR - dBc
10.6
2V SPAN, SINGLE-ENDED 1V SPAN, DIFFERENTIAL
67 66 65 64 63
60 1V SPAN, SINGLE-ENDED 55
9.8
8.9
1V SPAN, SINGLE-ENDED
50 2V SPAN, SINGLE-ENDED 45 1 100 10 FREQUENCY - MHz
8.1
62
7.3 1000
61 1
10 100 FREQUENCY - MHz
1000
TPC 7. SINAD/ENOB vs. Frequency
TPC 10. SNR vs. Frequency
-45 -50 -55 -60 1V SPAN, SINGLE-ENDED 2V SPAN, SINGLE-ENDED
95 90 85 80 1V SPAN, DIFFERENTIAL
-65
SFDR - dBc
THD - dBc
75 70 65 60 55 2V SPAN, SINGLE-ENDED
2V SPAN, DIFFERENTIAL
-70 -75 -80 -85 1V SPAN, DIFFERENTIAL 2V SPAN, DIFFERENTIAL
1V SPAN, SINGLE-ENDED
50 45 1000 100 10 FREQUENCY - MHz
-90 1 100 10 FREQUENCY - MHz
1
1000
TPC 8. THD vs. Frequency
TPC 11. SFDR vs. Frequency
72 -40 C +25 C 70
-70 -72 -74 -76
SNR - dBc
+85 C
THD - dBc
68
-78 +85 C -80 -82 -84 +25 C
66
64
-86 -88 -40 C 1 10 FREQUENCY - MHz 100
62 1 100 10 FREQUENCY - MHz 1000
-90
TPC 9. SNR vs. Temperature and Frequency
TPC 12. THD vs. Temperature and Frequency
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AD9226
105
70.5
4th HARMONIC 95
70.25
fIN = 2MHz
HARMONICS - dBc
70
85
SINAD - dBc
fIN = 12MHz
69.75
3RD HARMONIC 75
69.5 fIN = 20MHz
65 2ND HARMONIC
69.25
55 1 100 10 FREQUENCY - MHz 1000
69 10
20
30 40 50 SAMPLE RATE - MSPS
60
70
TPC 13. Harmonics vs. Frequency
TPC 16. SINAD vs. Sample Rate
100
90 85
SFDR - CLOCK STABILIZER ON
95
SINAD/SFDR - dBc
80
SFDR - CLOCK STABILIZER OFF SINAD - CLOCK STABILIZER ON
fIN = 2MHz
75 70 65 60 55
SFDR - dBc
fIN = 12MHz 90
85 fIN = 20MHz
SINAD - CLOCK STABILIZER OFF
50
80 10 20 30 40 50 SAMPLE RATE - MSPS 60 70
45 30
35
40
50 55 45 60 % POSITIVE DUTY CYCLE
65
70
TPC 14. SFDR vs. Sample Rate
TPC 17. SINAD/SFDR vs. Duty Cycle @ fIN = 20 MHz
70.5
1 0.8
70.25
fIN = 2MHz
0.6 0.4
70
SINAD - dBc
69.75
DNL - LSB
fIN = 12MHz
0.2 0 -0.2 -0.4
69.5 fIN = 20MHz 69.25
-0.6 -0.8
69 10
20
30 40 50 SAMPLE RATE - MSPS
60
70
-1
0
500
1k
1500
2k 2500 CODE
3k
3500
4k
TPC 15. Typical INL
TPC 18. Typical DNL
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AD9226-Typical IF Sampling Performance Characteristics AD9226
(AVDD = 5.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS with CLK Stabilizer Enabled, TA = 25 C, 2 V Differential Input Span, VCM = 2.5 V, AIN = -6.5 dBFS, VREF = 2.0 V, unless otherwise noted.)
0 -10 -20 -30 -40
dBFS
SNR/SFDR - dBFS
95
170.1
SNR = 70.2dBFS SFDR = 89dBFS NOISE FLOOR = 145.33dBFS/Hz
90
SFDR - 2V SPAN
165.1
NOISE FLOOR - dBFS/Hz
85
160.1
-50 -60 -70 -80 -90 -100 -110 -120 0 4 8 12 16 20 24 28 32
80
155.1
75
SNR/NOISE FLOOR - 2V SPAN
150.1
70
145.1
65 -24
-21
-18
-15 AIN - dBFS
-12
-9
140.1 -6
FREQUENCY - MHz
TPC 19. Dual-Tone 8K FFT with fIN-1 = 44.2 MHz and fIN-2 = 45.6 MHz
TPC 22. Dual-Tone SNR and SFDR with fIN-1 = 44.2 MHz and fIN-2 = 45.6 MHz
0 -10 -20 -30 -40
dBFS
90
165.1 SFDR - 2V SPAN
SNR = 68.5dBFS SFDR = 75dBFS NOISE FLOOR = 143.6dBFS/Hz
85
160.1
NOISE FLOOR - dBFS/Hz
SNR/SFDR - dBFS
80 SFDR - 1V SPAN 75 SNR/NOISE FLOOR - 2V SPAN 70
155.1
-50 -60 -70 -80 -90
150.1
145.1
-100 -110 -120 0 4 8 12 16 20 24 28 32
65 SNR/NOISE FLOOR - 1V SPAN 60 -24 -21 -18 -15 AIN - dBFS -12 -9
140.1
135.1 -6
FREQUENCY - MHz
TPC 20. Dual-Tone 8K FFT with fIN-1 = 69.2 MHz and fIN-2 = 70.6 MHz
TPC 23. Dual-Tone SNR and SFDR with fIN-1 = 69.2 MHz and fIN-2 = 70.6 MHz
0 -10 -20 -30 SNR = 67.5dBFS SFDR = 75dBFS NOISE FLOOR = 142.6dBFS/Hz
90 SFDR - 2V SPAN 85
165.1
160.1 NOISE FLOOR - dBFS/Hz
SNR/SFDR - dBFS
-40
dBFS
80
SFDR - 1V SPAN
155.1
-50 -60 -70 -80 -90 -100 -110 -120 0 4 8 12 16 20 24 28 32
75 SNR/NOISE FLOOR - 2V SPAN 70 SNR/NOISE FLOOR - 1V SPAN 65
150.1
145.1
140.1
60 -24
-21
-18
-15 AIN - dBFS
-12
-9
135.1 -6
FREQUENCY - MHz
TPC 21. Dual-Tone 8K FFT with fIN-1 = 139.2 MHz and fIN-2 = 140.7 MHz
TPC 24. Dual-Tone SNR and SFDR with fIN-1 = 139.2 MHz and fIN-2 = 140.7 MHz
-12-
REV. 0
AD9226
0 -10 -20 -30
SNR/SFDR - dBFS
90
165.1 SFDR - 2V SPAN
fIN = 190.82MHz fSAMPLE = 61.44MSPS
85
160.1
NOISE FLOOR - dBFS/Hz NOISE FLOOR - dBFS/Hz
-40
dBFS
80 SFDR - 1V SPAN 75 SNR/NOISE FLOOR - 2V SPAN 70
155.1
-50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 FREQUENCY - MHz 25 30
150.1
145.1
65 SNR/NOISE FLOOR - 1V SPAN 60 -24 -21 -18 -15 AIN - dBFS -12 -9
140.1
135.1 -6
TPC 25. Single-Tone 8K FFT at IF = 190 MHz-WCDMA (fIN = 190.82 MHz, fSAMPLE = 61.44 MSPS)
TPC 28. Single-Tone SNR and SFDR vs. AIN at IF = 190 MHz -WCDMA (fIN-1 = 190.8 MHz, fSAMPLE = 61.44 MSPS)
0 -10 -20 -30 SNR = 65.1dBFS SFDR = 59dBFS NOISE FLOOR = 140.2dBFS/Hz
85 SFDR - 2V SPAN 80
160.1
155.1
SNR/SFDR - dBFS
-40
75 SNR/NOISE FLOOR - 2V SPAN 70
SFDR - 1V SPAN
150.1
dBFS
-50 -60 -70 -80 -90 -100 -110 -120 0 4 8 12 16 20 24 28 32
145.1
65 SNR/NOISE FLOOR - 1V SPAN
140.1
60
135.1
55 -24
-21
-18
FREQUENCY - MHz
-15 AIN - dBFS
-12
-9
-6
130.1
TPC 26. Dual-Tone 8K FFT with fIN-1 = 239.1 MHz and fIN-2 = 240.7 MHz
TPC 29. Dual-Tone SNR and SFDR with fIN-1 = 239.1 MHz and fIN-2 = 240.7 MHz
-35
-45
-55
CMRR - dBc
-65
INPUT SPAN = 2V p-p
-75
-85
INPUT SPAN = 1V p-p
-95
1
10 100 FREQUENCY - MHz
1000
TPC 27. CMRR vs. Frequency (AIN = -0 dBFS and CML = 2.5 V)
REV. 0
-13-
AD9226
THEORY OF OPERATION
The AD9226 is a high-performance, single-supply 12-bit ADC. The analog input of the AD9226 is very flexible allowing for both single-ended or differential inputs of varying amplitudes that can be ac- or dc-coupled. It utilizes a nine-stage pipeline architecture with a wideband, sample-and-hold amplifier (SHA) implemented on a costeffective CMOS process. A patented structure is used in the SHA to greatly improve high frequency SFDR/distortion. This also improves performance in IF undersampling applications. Each stage of the pipeline, excluding the last stage, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier amplifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. Factory calibration ensures high linearity and low distortion.
ANALOG INPUT OPERATION
and/or shunt capacitor can help limit the wideband noise at the ADC's input by forming a low-pass filter. The source impedance driving VINA and VINB should be matched. Failure to provide matching will result in degradation of the AD9226's SNR, THD, and SFDR.
CH QS2 CPIN VINA VINB CPAR QS1 QS1 CPIN CPAR QH1 CS CS QS2 CH
Figure 3. Equivalent Input Circuit
VCC RS 33 VINA RS 33 15pF VINB VREF 10 F 0.1 F SENSE REFCOM
AD9226
Figure 3 shows the equivalent analog input of the AD9226 which consists of a 750 MHz differential SHA. The differential input structure of the SHA is highly flexible, allowing the device to be easily configured for either a differential or single-ended input. The analog inputs, VINA and VINB, are interchangeable with the exception that reversing the inputs to the VINA and VINB pins results in a data inversion (complementing the output word). The optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 2 V input span) and matched input impedance for VINA and VINB. Only a slight degradation in dc linearity performance exists between the 2 V and 1 V input spans. High frequency inputs may find the 1 V span better suited to achieve superior SFDR performance. (See Typical Performance Characteristics.) The ADC samples the analog input on the rising edge of the clock input. During the clock low time (between the falling edge and rising edge of the clock), the input SHA is in the sample mode; during the clock high time it is in hold. System disturbances just prior to the rising edge of the clock and/or excessive clock jitter on the rising edge may cause the input SHA to acquire the wrong value and should be minimized. When the ADC is driven by an op amp and a capacitive load is switched onto the output of the op amp, the output will momentarily drop due to its effective output impedance. As the output recovers, ringing may occur. To remedy the situation, a series resistor can be inserted between the op amp and the SHA input as shown in Figure 4. A shunt capacitance also acts like a charge reservoir, sinking or sourcing the additional charge required by the hold capacitor, CH, further reducing current transients seen at the op amp's output. The optimum size of this resistor is dependent on several factors, including the ADC sampling rate, the selected op amp, and the particular application. In most applications, a 30 to 100 resistor is sufficient. For noise-sensitive applications, the very high bandwidth of the AD9226 may be detrimental and the addition of a series resistor
VEE
Figure 4. Series Resistor Isolates Switched-Capacitor SHA Input from Op Amp; Matching Resistors Improve SNR Performance
OVERVIEW OF INPUT AND REFERENCE CONNECTIONS
The overall input span of the AD9226 is equal to the potential at the VREF pin. The VREF potential may be obtained from the internal AD9226 reference or an external source (see Reference Operation section). In differential applications, the center point of the span is obtained by the common-mode level of the signals. In singleended applications, the center point is the dc potential applied to one input pin while the signal is applied to the opposite input pin. Figures 5a-5f show various system configurations.
DRIVING THE ANALOG INPUTS
The AD9226 has a very flexible input structure allowing it to interface with single-ended or differential input interface circuitry. The optimum mode of operation, analog input range, and associated interface circuitry will be determined by the particular applications performance requirements as well as power supply options.
DIFFERENTIAL DRIVER CIRCUITS
Differential operation requires that VINA and VINB be simultaneously driven with two equal signals that are 180 out of phase with each other. Differential modes of operation (ac- or dc-coupled input) provide the best THD and SFDR performance over a wide frequency range. They should be considered for the most demanding spectral-based applications (e.g., direct IF conversion to digital). REV. 0
-14-
AD9226
1.5V 0.5V 33 15pF 33 1V VREF 10 F
0.1 F VINB
2.5V
AD9226
VINA 0.1 F CAPT
49.9
CMLEVEL 3.0V 2.5V 2.0V 0.1 F 33 15pF 33
VINB
AD9226 (LQFP)
VINA 0.1 F CAPT 0.1 F VREF CAPB 10 F
0.1 F CAPB
10 F
2V 3.0V 2.5V 2.0V 10 F
0.1 F
SENSE REFCOM
0.1 F
0.1 F SENSE
Figure 5a. 1 V Single-Ended Input, Common-Mode Voltage = 1 V
Figure 5e. 2 V Differential Input, Common-Mode Voltage = 2.5 V
1.25V 0.75V 33 15pF 33 1V 1.25V 0.75V 10 F
0.1 F VINB
AD9226
VINA
10k 10k
49.9
0.1 F CAPT 0.1 F 10 F
2.75V 2.5V 2.0V 2.5V 0.1 F
AVDD
AD9226
33 VINA
49.9
VREF
CAPB 0.1 F
15pF 33
VINB
0.1 F CAPT 0.1 F VREF CAPB 10 F
SENSE
1V 2.75V 2.5V 2.25V 10 F
0.1 F
Figure 5b. 1 V Differential Input, Common-Mode Voltage = 1 V
0.1 F SENSE
2.5V 1.5V 33
49.9
AD9226
VINA 15pF 0.1 F
VINB
Figure 5f. 1 V Differential Input, Common-Mode Voltage = 2.5 V (Recommended for IF Undersampling)
33 2V 2.5V 1.5V 10 F
0.1 F
CAPT 0.1 F 10 F
The differential input characterization for this data sheet was performed using the configuration shown in Figure 7. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform a singleended-to-differential conversion. In systems that do not need to be dc-coupled, an RF transformer with a center tap is the best method to generate differential inputs for the AD9226. It provides all the benefits of operating the ADC in the differential mode without contributing additional noise or distortion. An RF transformer also has the added benefit of providing electrical isolation between the signal source and the ADC. An improvement in THD and SFDR performance can be realized by operating the AD9226 in the differential mode. The performance enhancement between the differential and single-ended mode is most noteworthy as the input frequency approaches and goes beyond the Nyquist frequency (i.e., fIN > FS /2). The circuit shown in Figure 6a is an ideal method of applying a differential dc drive to the AD9226. It uses an AD8138 to derive a differential signal from a single-ended one. Figure 6b illustrates its performance. Figure 7 presents the schematic of the suggested transformer circuit. The circuit uses a Minicircuits RF transformer, model T1-1T, which has an impedance ratio of four (turns ratio of 2). The schematic assumes that the signal source has a 50 source impedance. The center tap of the transformer provides a convenient means of level-shifting the input signal to a desired common-mode voltage. In Figure 7 the transformer centertap is connected to a resistor divider at the midsupply voltage. -15-
VREF CAPB 0.1 F SENSE
Figure 5c. 2 V Differential Input, Common-Mode Voltage = 2 V
3.0V 1.0V 33 15pF 33 2V VREF 10 F
0.1 F VINB
AD9226
VINA 0.1 F CAPT 0.1 F CAPB 0.1 F 10 F
SENSE REFCOM
Figure 5d. 2 V Single-Ended Input, Common-Mode Voltage = 2 V
REV. 0
AD9226
SINGLE-ENDED DRIVER CIRCUITS
1V p-p 4.7 F 1k 499 450 49 499 49 499 VIN B AD8138 15pF 0.1 F 1k 49 VIN A CAPT 0.1 F
AD9226
CAPB
0.1 F
10 F
0.1 F
The AD9226 can be configured for single-ended operation using dc- or ac-coupling. In either case, the input of the ADC must be driven from an operational amplifier that will not degrade the ADC's performance. Because the ADC operates from a single supply, it will be necessary to level-shift ground-based bipolar signals to comply with its input requirements. Both dc- and ac-coupling provide this necessary function, but each method results in different interface issues which may influence the system design and performance. Single-ended operation requires that VINA be ac- or dc-coupled to the input signal source, while VINB of the AD9226 be biased to the appropriate voltage corresponding to the middle of the input span. The single-ended specifications for the AD9226 are characterized using Figure 9a circuitry with input spans of 1 V and 2 V. The common-mode level is 2.5 V. If the analog inputs exceed the supply limits, internal parasitic diodes will turn on. This will result in transient currents within the device. Figure 8 shows a simple means of clamping an input. It uses a series resistor and two diodes. An optional capacitor is shown for ac-coupled applications. A larger series resistor can be used to limit the fault current through D1 and D2. This can cause a degradation in overall performance. A similar clamping circuit can also be used for each input if a differential input signal is being applied. A better method to ensure the input is not overdriven is to use amplifiers powered by a single 5 V supply such as the AD8138.
Figure 6a. Direct-Coupled Drive Circuit with AD8138 Differential Op Amp
0 SNR = 66.9dBc SFDR = 70.0dBc -20
-40
dBc
-60
-80
-100
-120 0 4 8 12 16 MHz 20 24 28 32
Figure 6b. FS = 65 MSPS, fIN = 30 MHz, Input Span = 1 V p-p
VCC
OPTIONAL AC-COUPLING CAPACITOR RS1 30
AVDD D2 RS2 20
The same midsupply potential may be obtained from the CMLEVEL pin of the AD9226 in the LQFP package. Referring to Figure 7, a series resistor, RS, is inserted between the AD9226 and the secondary of the transformer. The value of 33 ohm was selected to specifically optimize both the THD and SNR performance of the ADC. RS and the internal capacitance help provide a low-pass filter to block high-frequency noise. Transformers with other turns ratios may also be selected to optimize the performance of a given application. For example, a given input signal source or amplifier may realize an improvement in distortion performance at reduced output power levels and signal swings. By selecting a transformer with a higher impedance ratio (e.g., Minicircuits T16-6T with a 1:16 impedance ratio), the signal level is effectively "stepped up" thus further reducing the driving requirements of signal source.
AVDD RS 33 1k 0.1 F VINA CAPT 49.9 0.1 F 1k 15pF
AD9226
D1 VEE
Figure 8. Simple Clamping Circuit
AC-COUPLING AND INTERFACE ISSUES
For applications where ac-coupling is appropriate, the op amp output can be easily level-shifted by means of a coupling capacitor. This has the advantage of allowing the op amp's common-mode level to be symmetrically biased to its midsupply level (i.e., (AVDD/2). Op amps that operate symmetrically with respect to their power supplies typically provide the best ac performance as well as greatest input/output span. Various highspeed performance amplifiers that are restricted to +5 V/-5 V operation and/or specified for 5 V single-supply operation can be easily configured for the 2 V or 1 V input span of the AD9226.
Simple AC Interface
AD9226
CAPB
0.1 F
10 F
MINICIRCUITS T1-1T
RS 33
VINB
0.1 F
Figure 7. Transformer-Coupled Input
Figure 9a shows a typical example of an ac-coupled, singleended configuration of the SSOP package. The bias voltage shifts the bipolar, ground-referenced input signal to approximately AVDD/2. The capacitors, C1 and C2, are 0.1 F ceramic and 10 F tantalum capacitors in parallel to achieve a low cutoff frequency while maintaining a low impedance over a wide frequency range. The combination of the capacitor and the resistor form a high-pass network with a high-pass -3 dB frequency determined by the equation, f-3 dB = 1/(2 x x R x (C1 + C2))
-16-
REV. 0
AD9226
The low-impedance VREF output can be used to provide dc bias levels to the fixed VINB pin and the signal on VINA. Figure 9b shows the VREF configured for 2.0 V, thus the input range of the ADC is 1.0 V to 3.0 V. Other input ranges could be selected by changing VREF. When the inputs are biased from the reference (Figure 9b), there may be a slight degeneration of dynamic performance. A midsupply output level is available at the CM LEVEL pin of the LQFP package.
+1V 0V -1V VIN +5V RS VINA -5V C2 0.1 F CAPT 15pF RS VINB 0.1 F 10 F R R VREF 3.5 2.5 1.5 0.1 F C1 10 F V R V R
Figure 10 illustrates the relation between common-mode voltage and THD. Note that optimal performance occurs when the reference voltage is set to 2.0 V (input span = 2.0 V).
DC-COUPLING AND INTERFACE ISSUES
Many applications require the analog input signal to be dc-coupled to the AD9226. An operational amplifier can be configured to rescale and level-shift the input signal to make it compatible with the selected input range of the ADC. The selected input range of the AD9226 should be considered with the headroom requirements of the particular op amp to prevent clipping of the signal. Many of the new high-performance op amps are specified for only 5 V operation and have limited input/output swing capabilities. Also, since the output of a dual supply amplifier can swing below absolute minimum (-0.3 V), clamping its output should be considered in some applications (see Figure 8). When single-ended, dc-coupling is needed, the use of the AD8138 in a differential configuration (Figure 9a) is highly recommended.
Simple Op Amp Buffer
AD9226
CAPB
0.1 F
10 F
0.1 F
10 F
0.1 F
Figure 9a. AC-Coupled Input Configuration
0.1 F VIN
In the simplest case, the input signal to the AD9226 will already be biased at levels in accordance with the selected input range. It is necessary to provide an adequately low source impedance for the VINA and VINB analog pins of the ADC.
REFERENCE OPERATION
10 F
RS VINA 1k
AD9226
0.1 F CAPT 15pF 0.1 F CAPB 10 F
1k RS VINB 10 F 0.1 F VREF 0.1 F
The AD9226 contains an on-board bandgap reference that provides a pin-strappable option to generate either a 1 V or 2 V output. With the addition of two external resistors, the user can generate reference voltages between 1 V and 2 V. See Figures 5a-5f for a summary of the pin-strapping options for the AD9226 reference configurations. Another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance described later in this section. Figure 11a shows a simplified model of the internal voltage reference of the AD9226. A reference amplifier buffers a 1 V fixed reference. The output from the reference amplifier, A1, appears on the VREF pin. The voltage on the VREF pin determines the full-scale input span of the ADC. This input span equals, Full-Scale Input Span = VREF The voltage appearing at the VREF pin, and the state of the internal reference amplifier, A1, are determined by the voltage appearing at the SENSE pin. The logic circuitry contains comparators that monitor the voltage at the SENSE pin. If the SENSE pin is tied to AVSS, the switch is connected to the internal resistor network thus providing a VREF of 2.0 V. If the SENSE pin is tied to the VREF pin via a short or resistor, the switch will connect to the SENSE pin. This connection will provide a VREF of 1.0 V. An external resistor network will provide an alternative VREF between 1.0 V and 2.0 V (see Figure 12). Another comparator controls internal circuitry that will disable the reference amplifier if the SENSE pin is tied to AVDD. Disabling the reference amplifier allows the VREF pin to be driven by an external voltage reference.
10 F
0.1 F
Figure 9b. Alternate AC-Coupled Input Configuration
-84 -83 -82 -81
dBc
-80 -79 -78 -77 -76 0 0.5 1.0 1.5 2.0 2.5 volts 3.0 3.5 4.0 4.5 5.0
Figure 10. THD vs. Common-Mode Voltage (2 V Differential Input Span, fIN = 10 MHz)
REV. 0
-17-
AD9226
AD9226
TO A/D CAPT 2.5V A2 CAPB
sets the input span to be 1.5 V p-p. The midscale voltage can also be set to VREF by connecting VINB to VREF. Alternatively, the midscale voltage can be set to 2.5 V by connecting VINB to a low-impedance 2.5 V source as shown in Figure 12.
3.25V 1.75V 2.5V 33 33 15pF
VINB
AD9226
VINA 0.1 F CAPT VREF SENSE REFCOM CAPB 0.1 F 0.1 F 10 F
VREF 1V A1
1.5V C1 0.1 F
10 F
0.1 F
R1 2.5k R2 5k
SENSE DISABLE A1 LOGIC REFCOM
Figure 12. Resistor Programmable Reference (1.5 V p-p Input Span, Differential Input VCM = 2.5 V)
USING AN EXTERNAL REFERENCE
Figure 11a. Equivalent Reference Circuit
0.1 F VREF 10 F 0.1 F CAPT 0.1 F 10 F
AD9226
CAPB
0.1 F
Figure 11b. CAPT and CAPB DC-Coupling
The AD9226 contains an internal reference buffer, A2 (see Figure 11b), that simplifies the drive requirements of an external reference. The external reference must be able to drive about 5 k ( 20%) load. Note that the bandwidth of the reference buffer is deliberately left small to minimize the reference noise contribution. As a result, it is not possible to rapidly change the reference voltage in this mode. Figure 13 shows an example of an external reference driving both VINB and VREF. In this case, both the common-mode voltage and input span are directly dependent on the value of VREF. Both the input span and the center of the input span are equal to the external VREF. Thus the valid input range extends from (VREF + VREF/2) to (VREF - VREF/2). For example, if the REF191, a 2.048 V external reference, is selected, the input span extends to 2.048 V. In this case, 1 LSB of the AD9226 corresponds to 0.5 mV. It is essential that a minimum of a 10 F capacitor, in parallel with a 0.1 F low-inductance ceramic capacitor, decouple the reference output to ground. To use an external reference, the SENSE pin must be connected to AVDD. This connection will disable the internal reference.
VINA+VREF/2 VINB-VREF/2 5V 0.1 F VREF
10 F
The actual reference voltages used by the internal circuitry of the AD9226 appear on the CAPT and CAPB pins. The voltages on these pins are symmetrical about the analog supply. For proper operation when using an internal or external reference, it is necessary to add a capacitor network to decouple these pins. Figure 11b shows the recommended decoupling network. The turn-on time of the reference voltage appearing between CAPT and CAPB is approximately 10 ms and should be evaluated in any power-down mode of operation.
USING THE INTERNAL REFERENCE
The AD9226 can be easily configured for either a 1 V p-p input span or 2 V p-p input span by setting the internal reference. Other input spans can be realized with two external gainsetting resistors as shown in Figure 12 of this data sheet, or using an external reference.
Pin Programmable Reference
33 15pF 33
AD9226
VINA 0.1 F
VINB
By shorting the VREF pin directly to the SENSE pin, the internal reference amplifier is placed in a unity-gain mode and the resultant VREF output is 1 V. By shorting the SENSE pin directly to the REFCOM pin, the internal reference amplifier is configured for a gain of 2.0 and the resultant VREF output is 2.0 V. The VREF pin should be bypassed to the REFCOM pin with a 10 F tantalum capacitor in parallel with a low-inductance 0.1 F ceramic capacitor as shown in Figure 11b.
Resistor Programmable Reference
CAPT 0.1 F CAPB 10 F
VREF
0.1 F
5V
SENSE
0.1 F
Figure 13. Using an External Reference
MODE CONTROLS Clock Stabilizer
Figure 12 shows an example of how to generate a reference voltage other than 1.0 V or 2.0 V with the addition of two external resistors. Use the equation, VREF = 1 V x (1 + R1/R2) to determine appropriate values for R1 and R2. These resistors should be in the 2 k to 10 k range. For the example shown, R1 equals 2.5 k and R2 equals 5 k. From the equation above, the resultant reference voltage on the VREF pin is 1.5 V. This
The clock stabilizer is a circuit that desensitizes the ADC from clock duty cycle variations. The AD9226 eases system clock constraints by incorporating a circuit that restores the internal duty cycle to 50%, independent of the input duty cycle. Low jitter on the rising edge (sampling edge) of the clock is preserved while the noncritical falling edge is generated on-chip. It may be desirable to disable the clock stabilizer, and may be necessary when the clock frequency speed is varied or completely
-18-
REV. 0
AD9226
stopped. Once the clock frequency is changed, over 100 clock cycles may be required for the clock stabilizer to settle to a different speed. When the stabilizer is disabled, the internal switching will be directly affected by the clock state. If the external clock is high, the SHA will be in hold. If the clock pulse is low, the SHA will be in track. TPC 16 shows the benefits of using the clock stabilizer. See Tables I and III.
Data Format Select (DFS) Table IV. Output Data Format
Binary Output Mode
0000 0000 0000 0000 0000 0000 1000 0000 0000 1111 1111 1111 1111 1111 1111
Input (V)
VINA-VINB VINA-VINB VINA-VINB VINA-VINB VINA-VINB
Condition (V)
< - VREF = - VREF =0 = + VREF - 1 LSB + VREF
Two's Complement Mode
1000 0000 0000 1000 0000 0000 0000 0000 0000 0111 1111 1111 0111 1111 1111
OTR
1 0 0 0 1
The AD9226 may be set for binary or two's complement data output formats. See Tables I and II.
SSOP Package
Out of Range (OTR)
The SSOP mode control (Pin 22) has two functions. It enables/ disables the clock stabilizer and determines the output data format. The exact functions of the mode pin are outlined in Table I.
Table I. Mode Select (SSOP)
Mode DNC AVDD GND 10 k Resistor
DFS Binary Binary Two's Complement Two's Complement To GND
Clock Duty Cycle Shaping Clock Stabilizer Disabled Clock Stabilizer Enabled Clock Stabilizer Enabled Clock Stabilizer Disabled
LQFP Package
Pin 35 of the LQFP package determines the output data format (DFS). If it is connected to AVSS, the output word will be straight binary. If it is connected to AVDD, the output data format will be two's complement. See Table II. Pin 43 of the LQFP package controls the clock stabilizer function of the AD9226. If the pin is connected to AVDD, both clock edges will be used in the conversion architecture. When Pin 43 is connected to AVSS, the internal duty cycle will be determined by the clock stabilizer function within the ADC. See Table III.
Table II. DFS Pin Controls
An out-of-range condition exists when the analog input voltage is beyond the input range of the converter. OTR is a digital output that is updated along with the data output corresponding to the particular sampled analog input voltage. Hence, OTR has the same pipeline delay (latency) as the digital data. It is LOW when the analog input voltage is within the analog input range. It is HIGH when the analog input voltage exceeds the input range as shown in Figure 14. OTR will remain HIGH until the analog input returns within the input range and another conversion is completed. By logical ANDing OTR with the MSB and its complement, overrange high or underrange low conditions can be detected. Table V is a truth table for the over/underrange circuit in Figure 15, which uses NAND gates. Systems requiring programmable gain conditioning of the AD9226 input signal can immediately detect an out-of-range condition, thus eliminating gain selection iterations. Also, OTR can be used for digital offset and gain calibration.
Table V. Out-of-Range Truth Table
OTR 0 0 1 1
OTR DATA OUTPUTS 1 0 0 1111 1111 1111 1111 1111 1111 1111 1111 1110
MSB 0 1 0 1
Analog Input Is In Range In Range Underrange Overrange
+FS - 1 1/2 LSB
DFS Function Straight Binary Two's Complement
Pin 35 Connection AVDD AVSS
OTR
-FS +1/2 LSB 0 0 1 0000 0000 0001 0000 0000 0000 0000 0000 0000 -FS -FS - 1/2 LSB +FS +FS - 1/2 LSB
Table III. Clock Stabilizer Pin
Clock Restore Function Clock Stabilizer Enabled Clock Stabilizer Disabled
Pin 43 Connection AVDD AVSS
Figure 14. OTR Relation to Input Voltage and Output Data
MSB OVER = 1
DIGITAL INPUTS AND OUTPUTS Digital Outputs
OTR MSB UNDER = 1
Table IV details the relationship among the ADC input, OTR, and straight binary output.
Figure 15. Overrange or Underrange Logic
REV. 0
-19-
AD9226
Digital Output Driver Considerations
The AD9226 output drivers can be configured to interface with 5 V or 3.3 V logic families by setting DRVDD to 5 V or 3.3 V respectively. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause glitches on the supplies and may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fan outs may require external buffers or latches.
OEB Function (Three-State)
3. The inherent distributed capacitor formed by the power plane, PCB insulation, and ground plane. It is important to design a layout that prevents noise from coupling onto the input signal. Digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. While the AD9226 features separate analog and driver ground pins, it should be treated as an analog component. The AVSS and DRVSS pins must be joined together directly under the AD9226. A solid ground plane under the ADC is acceptable if the power and ground return currents are carefully managed.
The LQFP-packaged AD9226 has Three-State (OEB) ability. If the OEB pin is held low, the output data drivers are enabled. If the OEB pin is high, the output data drivers are placed in a high impedance state. It is not intended for rapid access to buss.
Clock Input Considerations
AVDD 10 F 0.1 F
AD9226
AVSS
High-speed, high-resolution ADCs are sensitive to the quality of the clock input. The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic performance of the AD9226. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low-jitter crystal controlled oscillators make the best clock sources. The quality of the clock input, particularly the rising edge, is critical in realizing the best possible jitter performance of the part. Faster rising edges often have less jitter.
Clock Input and Power Dissipation
Figure 17. Analog Supply Decoupling
Analog and Digital Driver Supply Decoupling
Most of the power dissipated by the AD9226 is from the analog power supplies. However, lower clock speeds will reduce digital current. Figure 16 shows the relationship between power and clock rate.
600
The AD9226 features separate analog and digital supply and ground pins, helping to minimize digital corruption of sensitive analog signals. In general, AVDD (analog power) should be decoupled to AVSS (analog ground). The AVDD and AVSS pins are adjacent to one another. Also, DRVDD (digital power) should be decoupled to DRVDD (digital ground). The decoupling capacitors (especially 0.1 f) should be located as close to the pins as possible. Figure 17 shows the recommended decoupling for the pair of analog supplies; 0.1 F ceramic chip and 10 F tantalum capacitors should provide adequately low impedance over a wide frequency range.
CML 0.1 F VR
AD9226
0.1 F
550
POWER DISSIPATION - mW
500 DRVDD = 5V 450 400 DRVDD = 3V 350 300 250 200 5 15 25 35 45 55 65 75 SAMPLE RATE - Msps
Figure 18. CML Decoupling (LQFP)
Bias Decoupling
The CML and VR are analog bias points used internally by the AD9226. These pins must be decoupled with at least a 0.1 F capacitor as shown in Figure 18. The dc level of CML is approximately AVDD/2. This voltage should be buffered if it is to be used for any external biasing. CML and VR outputs are only available in the LQFP package.
DRVDD 10 F 0.1 F
AD9226
DRVSS
Figure 16. Power Consumption vs. Sample Rate
GROUNDING AND DECOUPLING Analog and Digital Grounding
Figure 19. Digital Supply Decoupling
CML
Proper grounding is essential in any high-speed, high-resolution system. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power schemes. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths.
The LQFP-packaged AD9226 has a midsupply reference point. This midsupply point is used within the internal architecture of the AD9226 and must be decoupled with a 0.1 F capacitor. It will source or sink a load of up to 300 A. If more current is required, it should be buffered with a high impedance amplifier.
-20-
REV. 0
AD9226
VR
VR is an internal bias point on the LQFP package. It must be decoupled to ground with a 0.1 F capacitor. The digital activity on the AD9226 chip falls into two general categories: correction logic and output drivers. The internal correction logic draws relatively small surges of current, mainly during the clock transitions. The output drivers draw large current impulses while the output bits are changing. The size and duration of these currents are a function of the load on the output bits: large capacitive loads are to be avoided. For the digital decoupling shown in Figure 19, 0.1 F ceramic chip and 10 F tantalum capacitors are appropriate. Reasonable capacitive loads on the data pins are less than 20 pF per bit. Applications involving greater digital loads should consider increasing the digital decoupling proportionally and/or using external buffers/latches. A complete decoupling scheme will also include large tantalum or electrolytic capacitors on the power supply connector to reduce low-frequency ripple to negligible levels.
EVALUATION BOARD AND TYPICAL BENCH CHARACTERIZATION TEST SETUP
S3 connector. The various input signal options are accessible by the jumper connections. Refer to the Evaluation Board schematic. The clock input signal to the AD9226 evaluation board can be applied to one of two inputs, CLOCK and AUXCLK. The CLOCK input should be selected if the frequency of the input clock signal is at the target sample rate of the AD9226. The input clock signal is ac-coupled and level-shifted to the switching threshold of a 74VHC02 clock driver. The AUXCLK input should be selected in applications requiring the lowest jitter and SNR performance (i.e., IF Undersampling characterization). It allows the user to apply a clock input signal that is 4x the target sample rate of the AD9226. A low-jitter, differential divide-by-4 counter, the MC100EL33D, provides a 1x clock output that is subsequently returned back to the CLOCK input via JP7. For example, a 260 MHz signal (sinusoid) will be divided down to a 65 MHz signal for clocking the ADC. Note, R1 must be removed with the AUXCLK interface. Lower jitter is often achieved with this interface since many RF signal generators display improved phase noise at higher output frequencies and the slew rate of the sinusoidal output signal is 4x that of a 1x signal of equal amplitude. Figure 20 shows the bench characterization setup used to evaluate the AD9226's ac performance for many of the data sheet characterization curves. Signal and Clock RF generators A and B are high-frequency, "very" low-phase noise frequency sources. These generators should be phase locked by sharing the same 10 MHz REF signal (located on the instruments back panel) to allow for nonwindowed, coherent FFTs. Also, the AUXCLK option on the AD9226 evaluation board should be used to achieve the best SNR performance. Since the distortion and broadband noise of an RF generator can often be a limiting factor in measuring the true performance of an ADC, a high Q passive bandpass filter should be inserted between the generator and AD9226 evaluation board.
5V 5V 3V 3V
The AD9226 evaluation board is configured to operate upon applying both power and the analog and clock input signals. It provides three possible analog input interfaces to characterize the AD9226's ac and dc performance. For ac characterization, it provides a transformer coupled input with the common-mode input voltage (CMV) set to AVDD/2. Note, the evaluation board is shipped with a transformer coupled interface and a 2 V input span. For differential dc coupled applications, the evaluation board has provisions to be driven by the AD8138 amplifier. If a single-ended input is desired, it may be driven through the
AVDD REFIN SIGNAL SYNTHESIZER 65(OR 260 MHz), 4V p-p HP8644 1 MHz BANDPASS FILTER S4 INPUT xFMR
GND
DUT GND AVDD
DUT DVDD
DVDD
AD9226
EVALUATION BOARD
OUTPUT WORD (P1)
DSP EQUIPMENT
10 MHz REFOUT
CLK SYNTHESIZER 65(OR 260 MHz), 4V p-p HP8644
S1 INPUT CLOCK
S4 AUX CLOCK ( 4)
Figure 20. Evaluation Board Connections
REV. 0
-21-
AD9226
TP5 WHT DUTAVDD JP23 JP22 C1 10 F 10V C36 0.1 F C39 0.001 F 3 4 1 C35 0.1 F 2 36 37 C34 0.1 F C20 10 F 10V C32 0.1 F C50 0.1 F FBEAD 2 C58 22 F 25V L1 1 TP2 RED DUTAVDD VINA SHEET 3 VINB C33 0.1 F 38 39 40 41 42 45 46 47 5 6 32 33 DUTAVDD FBEAD 2 C47 22 F 25V L2 1 TP1 RED AVDD C23 10 F 10V C38 0.1 F C41 0.001 F 31 34 30 29 23 22 FBEAD 2 C48 22 F 25V L3 1 TP3 RED DUTDRVDD DUTDRVDD C3 10 F 10V C37 0.1 F C40 0.001 F NC = NO CONNECT FBEAD 2 C6 22 F 25V L4 1 TP4 RED DVDD TP11 TP12 TP13 TP14 BLK BLK BLK BLK
R3 10k
JP25
AD9226LQFP
AVDD1 AVDD2 AVSS1 AVSS2 SENSE VREF REFCOM CAPB1 CAPB2 CAPT1 CAPT2 CML VINA VINB NC1 NC2 AVSS3 AVSS4 AVDD3 AVDD4 DRVSS3 DRVDD3 DRVDD1 DRVSS1 OTR MSB-B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
28 27 26 25 24 21 20 19 18 17 16 13 12 11 10 8 9 48 35 43 7 44 15 14
OTR0 D130 D120 D110 D100 D90 D80 D70 D60 D50 D40 D30 D20 D10 D00 JP1 JP2 AVDD JP6
JP24 R4 10k C21 10 F 10V
U1
B11 B12 B13
DUTAVDDIN TB1 2
LSB-B14 NC3 OEB VR DFS DUTY CLK NC4 DRVDD2 DRVSS2
C59 0.1 F
AGND TB1 3
R42 1k R6 1k R10 1k DUTCLK WHT TP6
C2 0.1 F
AVDDIN TB1 1
C52 0.1 F
DRVDDIN TB1 5
C53 0.1 F
AGND TB1 4
DVDDIN TB1 6
C14 0.1 F
Figure 21. AD9226 Evaluation Board
-22-
REV. 0
AD9226
C12 0.1 F 10V C4 10 F 1 2 1 74VHC541 20 AUXCLK S5 1 2 R11 49.9
G1 G2 VCC
DVDD
6 5 4
T1-1T
1N5712 1 2 D2 2 D1 1N5712 2 D13 D12 D11 D10 D9
19
GND Y1 Y2
10 18 17 16 15 14 13 12 11
RP1 1 22 16 RP1 2 22 15 RP1 3 22 14 RP1 4 22 13 RP1 5 22 12 RP1 6 22 11 RP1 7 22 10 RP1 8 22 9 RP2 1 22 16 RP2 2 22 15 RP2 3 22 14 RP2 4 22 13 RP2 5 22 12 RP2 6 22 11
1 P1 3 P1 5 P1 7 P1 9 P1 11 P1 13 P1 15 P1 17 P1 19 P1 21 P1 23 P1 25 P1 27 P1 29 P1 31 P1
P1 2 P1 4 P1 6 P1 8 P1 10 P1 12 P1 14 P1 16 P1 18 P1 20 P1 22 P1 24 P1 26 P1 28 P1 30 P1 32 P1 34 P1 36 P1 38 P1 40
2 3 4 5 6 7 8 9
A1 A2 A3 A4 A5 A6 A7 A8
T2
3
U6
Y3 Y4 Y5 Y6 Y7 Y8
AVDD
8 7 6 5
MC100EL33D
VCC OUT REF VEE NC
1 2 3 4
D8 D7 D6
U3
INA INB
INCOM
AVDD R12 113 R14 90 JP7 C17 0.1 F
AVDD R13 113 R15 90
AVDD C18 0.1 F C19 0.1 F U3 DECOUPLING C26 10 F 10V
C11 0.1 F 10V C5 10 F 1 2 1 74VHC541 20
G1 G2 VCC
19
GND Y1 Y2
10 18 17 16 15 14 13 12 11
D5 R19 4k R2 5k JP17
B
2 3 4 5 6 7 8 9
A1 A2 A3 A4 A5 A6 A7 A8
R18 4k
D4 AVDD D3 D2 D1 11 8b R7 DUTCLK 10 22 R9 22 D0 OTR
U7
Y3 Y4 Y5 Y6 Y7 Y8
CLOCK S1 1 2
1 A 2 TP7 C13 WHT 8a 0.10 F 13 12 R1 49.9 74VHC04
3
74VHC04 JP4 1 8c 2 JP3
RP2 8 22 9
33 P1 35 P1
9
8d
74VHC04 8 AVDD C10 0.1 F U8 DECOUPLING C3 10 F 10V
74VHC04 5 8e 6
37 P1 RP2 7 22 10 NC = NO CONNECT 39 P1
74VHC04 3 8f 4
74VHC04
Figure 22. AD9226 Evaluation Board
REV. 0
-23-
AD9226
OTRO D130 D120 D110 RP3 8 1 22 RP3 7 2 22 RP3 6 3 22 RP3 5 4 22 RP4 22 8 RP4 22 7 RP4 22 6 RP4 22 5 OTR D13 D12 D11 C15 10 F 10V 1 2 C69 0.1 F R37 499 3 1
VCC -W
JP5 SINGLE INPUT S3 1 2 R5 49.9 AVDD C9 0.33 F R40 1k R41 1k C7 0.1 F JP42
D100 D90 D80 D70
1 2 3 4
D10 D9 D8 D7
AVDD
AVDD R32 10k C8 0.1 F
JP40 R21 22 R22 22 C44 TBD VINA C24 SHEET 1 50pF VINB C43 TBD
JP45 JP46
R33 10k
JP41
R34 523 AMP INPUT S2 1 2 R35 499 R31 49.9
JP43 4
VO VDC VO-
U2
8
W VEE
2
D60 D50 XFMR INPUT S4 1 2 R24 49.9 DUTAVDD 6 5 4
5
RP5 8 1 22 RP5 2 22 7 RP5 6 3 22 RP5 5 4 22
D6 D5 D4
AD8138
R36 499
6
T1-1T
1 2
R38 1k R8 1k C25 0.33 F C16 0.1 F
D40
T2
3
D30 D20 D10 D00
RP6 8 1 22 RP6 7 2 22 RP6 6 3 22 RP6 5 4 22
D3 D2 D1 D0
Figure 23. AD9226 Evaluation Board
Figure 24. Evaluation Board Component Side Layout (Not to Scale)
-24-
REV. 0
AD9226
Figure 25. Evaluation Board Solder Side Layout (Not to Scale)
Figure 26. Evaluation Board Power Plane
REV. 0
-25-
AD9226
Figure 27. Evaluation Board Ground Plane
Figure 28. Evaluation Board Component Side (Not to Scale)
-26-
REV. 0
AD9226
Figure 29. Evaluation Board Solder Side (Not to Scale)
REV. 0
-27-
AD9226
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Shrink Small Outline (RS-28)
0.407 (10.34) 0.397 (10.08)
48-Lead Thin Plastic Quad Flatpack (ST-48)
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45)
0.354 (9.00) BSC SQ
48 1 37 36
28
15
TOP VIEW
(PINS DOWN)
0.276 (7.00) BSC SQ
25
1
14
COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09)
0 MIN
12 13 24
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.019 (0.5) BSC 7 0
0.011 (0.27) 0.006 (0.17) 0.057 (1.45) 0.053 (1.35)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC
8 0.015 (0.38) 0 SEATING 0.009 (0.229) 0.010 (0.25) PLANE 0.005 (0.127)
0.03 (0.762) 0.022 (0.558)
0.006 (0.15) SEATING 0.002 (0.05) PLANE
-28-
REV. 0
PRINTED IN U.S.A.
C01027-3-7/00 (rev. 0)
0.311 (7.9) 0.301 (7.64)
0.212 (5.38) 0.205 (5.21)

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